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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_MMFR0, Memory Model Feature Register 0</h1><p>The ID_MMFR0 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the implemented memory model and memory management support in AArch32 state.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_MMFR0 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_mmfr0_el1.html">ID_MMFR0_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_MMFR0 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_MMFR0 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">InnerShr</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">FCSE</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">AuxReg</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">TCM</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">ShareLvl</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">OuterShr</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">PMSA</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">VMSA</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">InnerShr, bits [31:28]</h4><div class="field">
      <p>Innermost Shareability. Indicates the innermost shareability domain implemented. Defined values are:</p>
    <table class="valuetable"><tr><th>InnerShr</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Implemented as Non-cacheable.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Implemented with hardware coherency support.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Shareability ignored.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, and <span class="binarynumber">0b1111</span>.</p>
<p>This field is valid only if the implementation supports two levels of shareability, as indicated by ID_MMFR0.ShareLvl having the value <span class="binarynumber">0b0001</span>.</p>
<p>When ID_MMFR0.ShareLvl is zero, this field is <span class="arm-defined-word">UNKNOWN</span>.</p></div><h4 id="fieldset_0-27_24">FCSE, bits [27:24]</h4><div class="field">
      <p>Indicates whether the implementation includes the FCSE. Defined values are:</p>
    <table class="valuetable"><tr><th>FCSE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support for FCSE.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-23_20">AuxReg, bits [23:20]</h4><div class="field">
      <p>Auxiliary Registers. Indicates support for Auxiliary registers. Defined values are:</p>
    <table class="valuetable"><tr><th>AuxReg</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support for Auxiliary Control Register only.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Support for Auxiliary Fault Status Registers (<a href="AArch32-aifsr.html">AIFSR</a> and <a href="AArch32-adfsr.html">ADFSR</a>) and Auxiliary Control Register.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0010</span>.</p>
<div class="note"><span class="note-header">Note</span><p>Accesses to unimplemented Auxiliary registers are <span class="arm-defined-word">UNDEFINED</span>.</p></div></div><h4 id="fieldset_0-19_16">TCM, bits [19:16]</h4><div class="field">
      <p>Indicates support for TCMs and associated DMAs. Defined values are:</p>
    <table class="valuetable"><tr><th>TCM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Support for TCM only, Armv6 implementation.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>Support for TCM and DMA, Armv6 implementation.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-15_12">ShareLvl, bits [15:12]</h4><div class="field">
      <p>Shareability Levels. Indicates the number of shareability levels implemented. Defined values are:</p>
    <table class="valuetable"><tr><th>ShareLvl</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>One level of shareability implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Two levels of shareability implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-11_8">OuterShr, bits [11:8]</h4><div class="field">
      <p>Outermost Shareability. Indicates the outermost shareability domain implemented. Defined values are:</p>
    <table class="valuetable"><tr><th>OuterShr</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Implemented as Non-cacheable.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Implemented with hardware coherency support.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Shareability ignored.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span>, <span class="binarynumber">0b0001</span>, and <span class="binarynumber">0b1111</span>.</p></div><h4 id="fieldset_0-7_4">PMSA, bits [7:4]</h4><div class="field">
      <p>Indicates support for a PMSA. Defined values are:</p>
    <table class="valuetable"><tr><th>PMSA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support for <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> PMSA.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Support for PMSAv6, with a Cache Type Register implemented.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>Support for PMSAv7, with support for memory subsections. Armv7-R profile.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-3_0">VMSA, bits [3:0]</h4><div class="field">
      <p>Indicates support for a VMSA. Defined values are:</p>
    <table class="valuetable"><tr><th>VMSA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Support for <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> VMSA.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>Support for VMSAv6, with Cache and TLB Type Registers implemented.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>Support for VMSAv7, with support for remapping and the Access flag. ARMv7-A profile.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>As for <span class="binarynumber">0b0011</span>, and adds support for the PXN bit in the Short-descriptor translation table format descriptors.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>As for <span class="binarynumber">0b0100</span>, and adds support for the Long-descriptor translation table format.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0101</span>.</p></div><div class="access_mechanisms"><h2>Accessing ID_MMFR0</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0001</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_MMFR0;
elsif PSTATE.EL == EL2 then
    R[t] = ID_MMFR0;
elsif PSTATE.EL == EL3 then
    R[t] = ID_MMFR0;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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